Exceptions And The Pipeline - Analog Devices ADSP-BF53x Blackfin Reference

• The
EXCAUSE
event code.
• The address of the offending instruction is saved in
the processor were executing, for example, the NMI handler, the
register would not have been updated; the excepting instruc-
RETN
tion address is always stored in
To determine whether an exception occurred while an exception handler
was executing, check
code indicating an "unrecoverable event" (
coverable event occurred, register
recent instruction to cause an exception. This mechanism is not intended
for recovery, but rather for detection.

Exceptions and the Pipeline

Interrupts and exceptions treat instructions in the pipeline differently.
• When an interrupt occurs, all instructions in the pipeline are
aborted.
• When an exception occurs, all instructions in the pipeline after the
excepting instruction are aborted. For error exceptions, the except-
ing instruction is also aborted.
Because exceptions, NMIs, and emulation events have a dedicated return
register, guarding the return address is optional. Consequently, the
and instructions for exceptions, NMIs, and emulation events do not
POP
affect the interrupt system.
Note, however, the return instructions for exceptions (
do clear the Least Significant Bit (LSB) currently set in
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
field in is updated with an unrecoverable
SEQSTAT
at the end of the exception handler for the
SEQSTAT
RETX
Program Sequencer
.
RETX
EXCAUSE = 0x25
holds the address of the most
RTX
IPEND
. Note if
RETX
). If an unre-
PUSH
, , and )
RTN RTE
.
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