Table of Contents
Advertisement
into the
register prior to jumping to the event vector. A typical inter-
RETI
rupt service routine terminates with an
sequencer to reload the Program Counter,
following example shows a simple interrupt service routine.
isr:
[--SP] = (R7:0, P5:0);
[--SP] = ASTAT;
/* place core of service routine here */
ASTAT = [SP++];
(R7:0, P5:0) = [SP++];
RTI;
/* return from interrupt */
isr.end:
There is no need to manage the
enabled. If however, nesting is enabled and the respective service routine
must be interruptible by an interrupt of higher priority, the
must be saved, most likely onto the stack.
Instructions that access the
reading the
RETI
nesting again. This enables the service routine to break itself down into
interruptible and non-interruptible sections. For example:
isr:
[--SP] = (R7:0, P5:0);
[--SP] = ASTAT;
/* place critical or atomic code here */
[--SP] = RETI;
/* place core of service routine here */
RETI = [SP++];
/* more critical or atomic instructions */
ASTAT = [SP++];
(R7:0, P5:0) = [SP++];
RTI;
/* return from interrupt */
isr.end:
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* push core registers */
/* push arithmetic status */
/* pop arithmetic status */
/* pop core registers */
RETI
register do have an implicit site effect—
RETI
register enables interrupt nesting. Writing to it disables
/* push core registers */
/* push arithmetic status */
/* enable nesting */
/* disable nesting */
/* pop arithmetic status */
/* pop core registers */
Program Sequencer
instruction that instructs the
RTI
, from the
PC
register when interrupt nesting is not
register. The
RETI
register
RETI
4-43
Advertisement
Table of Contents
