Add on Sign
General Form
dest_hi = dest_lo = SIGN (src0_hi) * src1_hi
Syntax
Dreg_hi = Dreg_lo = SIGN ( Dreg_hi ) * Dreg_hi
/* (b) */
Register Consistency
The destination registers
data register. Similarly,
register and
src1_hi
Syntax Terminology
:
Dreg_hi
R7–0.H
:
Dreg_lo
R7–0.L
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
+ SIGN (src0_lo) * src1_lo
+ SIGN ( Dreg_lo ) * Dreg_lo ;
and
dest_hi
dest_lo
and
src0_hi
src0_lo
and
must be halves of the same register.
src1_lo
Vector Operations
must be halves of the same
must be halves of the same
19-3