Core Synchronize - Analog Devices ADSP-BF53x Blackfin Reference

Core Synchronize

General Form
CSYNC
Syntax
CSYNC ; /* (a) */
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length.
Functional Description
The Core Synchronize (
ing core operations and the flushing of the core store buffer before
proceeding to the next instruction. Pending core operations include any
speculative states (for example, branch prediction) or exceptions. The core
store buffer lies between the processor and the L1 cache memory.
is typically used after core MMR writes to prevent imprecise
CCYNC
behavior.
Flags Affected
None
Required Mode
User & Supervisor
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
External Event Management
) instruction ensures resolution of all pend-
CSYNC
16-5