Analog Devices ADSP-BF53x Blackfin Reference page 156

Hardware Loops
Two sets of zero-overhead loop registers implement loops, using hardware
counters instead of software instructions to evaluate loop conditions. After
evaluation, processing branches to a new target address. Both sets of regis-
ters include the Loop Counter (
( ) registers.
LB
Table 4-11 describes the 32-bit loop register sets.
Table 4-5. Loop Registers
Registers
LC0, LC1
LT0, LT1
LB0, LB1
When an instruction at address
of , then the next instruction executed will be from the address in
LB0
In other words, when
A loopback only occurs when the count is greater than or equal to 2. If the
count is nonzero, then the count is decremented by 1. For example, con-
sider the case of a loop with two iterations. At the beginning, the count is
2. Upon reaching the first loop end, the count is decremented to 1 and the
program flow jumps back to the top of the loop (to execute a second
time). Upon reaching the end of the loop again, the count is decremented
to 0, but no loopback occurs (because the body of the loop has already
been executed twice).
The instruction can be used to load all three registers of a loop unit
LSETUP
at once. Each loop register can also be loaded individually with a register
transfer, but this incurs a significant overhead if the loop count is nonzero
(the loop is active) at the time of the transfer.
The following code example shows a loop that contains two instructions
and iterates 32 times.
4-22 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
LC
Description Function
Loop Counters Maintains a count of the remaining iterations of the loop
Loop Tops Holds the address of the first instruction within a loop
Loop Bottoms Holds the address of the last instruction of the loop
X
, then an implicit jump to
PC == LB0
), Loop Top ( ), and Loop Bottom
LT
is executed, and
X
matches the contents
LT0
is executed.
LT0
.