interrupts
NMI, return from (RTN instruction),
7-10
non-nested,
4-51
peripheral,
4-30
popping RETI from stack,
priority,
16-17
priority watermark,
6-35
processing, 4-3,
4-31
program flow,
4-2
return from interrupt (RTI) instruction,
7-10,
7-11
servicing,
4-48
shared,
4-37
sources, peripheral,
4-35
supported by CEC,
1-8
uninterruptable instructions, 7-11, 10-6,
10-15, 10-18,
16-23
vector,
16-17
interrupt service routine, determining
source of interrupt,
invalidation of instruction cache,
invalid data cache line, 6-34,
I/O memory space,
1-6
IPEND (core interrupts pending) register
IPRIO (interrupt priority) register,
IPRIO_MARK[0:3] (priority watermark)
field,
6-36
I-registers (index),
5-8
Ireg registers. See index registers
ISR (interrupt service routine)
multiple interrupt sources,
using hardware loops,
ITEST_COMMAND (instruction test
command) register,
ITEST_DATAx (instruction test data)
registers, 6-22,
17-2
IVGn bits, 4-39, 4-40,
IVHW (hardware error) bit, 4-39, 4-40,
4-41,
4-59
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(continued)
10-3
4-36
6-18
6-75
6-35
4-32
4-28
6-21
4-41
IVTMR (core timer interrupt) bit, 4-39,
4-40, 4-41,
4-47
J
JTAG port,
3-16
JUMP.0 (unknown) instruction,
JUMP instruction
conditional,
4-10
conditional jump,
7-5
contrasted with CALL,
indirect,
4-12
opcodes,
C-13
range,
4-11
syntax,
7-2
JUMP.L (long jump) instruction,
jumps, program flow,
4-1
JUMP.S (short jump) instruction,
L
L1 data
memory, defined,
1-5
memory controller registers,
SRAM,
6-27
L1 data cache bank select (DCBS) bit,
6-25, 6-26, 6-29,
L1 data memory configure (DMC[1:0])
field, 6-25, 6-27, 6-30,
L1 instruction memory configuration
(IMC) bit, 1-5, 6-6, 6-7,
L1 instruction memory controller registers,
B-4
L1 memory, 1-4,
1-5
See also level 1 (L1) memory; level 1 (L1)
data memory; level 1 (L1) instruction
memory
L1 scratchpad RAM, defined,
L2 (level 2) memory, defined,
L2 memory. See level 2 (L2) memory
latched interrupt request,
Index
4-11
4-10
4-11
4-11
B-1
6-31
6-38
6-19
1-5
1-5
4-39
I-19
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