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5 ADDRESS ARITHMETIC UNIT
Like most DSP and RISC platforms, the Blackfin processors have a
load/store architecture. Computation operands and results are always rep-
resented by core registers. Prior to computation, data is loaded from
memory into core registers and results are stored back by explicit move
operations. The Address Arithmetic Unit (AAU) provides all the required
support to keep data transport between memory and core registers effi-
cient and seamless. Having a separate arithmetic unit for address
calculations prevents the data computation block from being burdened by
address operations. Not only can the load and store operations occur in
parallel to data computations, but memory addresses can also be calcu-
lated at the same time.
The AAU uses Data Address Generators (DAGs) to generate addresses for
data moves to and from memory. By generating addresses, the DAGs let
programs refer to addresses indirectly, using a DAG register instead of an
absolute address.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Figure 5-1
shows the AAU block diagram.
5-1
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