Cache Hits And Misses - Analog Devices ADSP-BF53x Blackfin Reference

TAG - 20-BIT ADDRESS TAG
LRUPRIO - LRU PRIORITY BIT FOR LINE LOCKING
LRU - LRU STATE
V - VALID BIT
WD 3
WD - 64-BIT DATA WORD
Figure 6-5. Cache Line – Tag and Data Portions

Cache Hits and Misses

A cache hit occurs when the address for an instruction fetch request from
the core matches a valid entry in the cache. Specifically, a cache hit is
determined by comparing the upper 18 bits and bits 11 and 10 of the
instruction fetch address to the address tags of valid lines currently stored
in a cache set. The cache set (cache line across ways) is selected, using bits
9 through 5 of the instruction fetch address. If the address-tag compare
operation results in a match in any of the four ways and the respective
cache line is valid, a cache hit occurs. If the address-tag compare operation
does not result in a match in any of the four ways or the respective line is
not valid, a cache miss occurs.
When a cache miss occurs, the instruction memory unit generates a cache
line fill access to retrieve the missing cache line from memory that is exter-
nal to the core. The address for the external memory access is the address
of the target instruction word. When a cache miss occurs, the core halts
until the target instruction word is returned from external memory.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
TAG
WD 2 WD 1
LRUPRIO
LRU V
WD 0
Memory
6-13