Table of Contents
Advertisement
DCPLB_ADDRx Registers
Figure 6-21
shows the DCPLB Address registers (
DCPLB Address Registers (DCPLB_ADDRx)
For Memory-
mapped
addresses, see
Table
6-4.
Figure 6-21. DCPLB Address Registers
Table 6-4. DCPLB Address Register Memory-mapped Addresses
Register Name
DCPLB_ADDR0
DCPLB_ADDR1
DCPLB_ADDR2
DCPLB_ADDR3
DCPLB_ADDR4
DCPLB_ADDR5
DCPLB_ADDR6
DCPLB_ADDR7
DCPLB_ADDR8
DCPLB_ADDR9
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
Memory-mapped Address
0xFFE0 0100
0xFFE0 0104
0xFFE0 0108
0xFFE0 010C
0xFFE0 0110
0xFFE0 0114
0xFFE0 0118
0xFFE0 011C
0xFFE0 0120
0xFFE0 0124
DCPLB_ADDRx
0
0
0
0
0
0
0
X
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Memory
).
Reset = 0x0000 0000
Upper Bits of Address for
Match[21:6]
Upper Bits of Address for
Match[5:0]
6-59
Advertisement
Table of Contents
