Analog Devices ADSP-BF53x Blackfin Reference page 1032

Index
reset
effect on memory configuration,
event, 1-7
hardware, 3-12, 3-13
initialization sequence, for interrupts,
4-37
interrupt (RST), 4-46
MMU, 6-52
processor state upon reset,
state, 3-2, 3-10
system and core, 3-16
system software, 3-12,
watchdog timer, 3-12,
RESET pin, 4-46
RESET signal
de-asserting, 3-7
reset state, 3-10
reset values, ADSP-BF535,
resources, protected, 3-4
restoring loops, 4-27
resuming loops, 4-27
RETI (return from interrupt) register,
RETS (return from subroutine) register,
4-12, 7-9, 10-3, 10-17
return address
for CALL instruction,
registers, 4-6
storage, 4-3
return from emulation (RTE) instruction.
See RTE
return from exception (RTX) instruction.
See RTX
return from interrupt (RETI) register. See
RETI (return from interrupt) register
return from interrupt (RTI) instruction. See
RTI
return from NMI (RTN) instruction,
return from nonmaskable interrupt (RTN)
instruction, 7-11
I-30 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(continued)
6-26
3-11
3-14
3-14
A-1
10-3
4-10
7-10
return from nonmaskable interrupt (RTN)
instruction. See RTN
return from subroutine (RETS) register. See
RETS
return from subroutine (RTS) instruction.
See RTS
return instruction
defined, 4-10
invoking user mode,
opcodes, C-14
supervisor mode, 3-7
syntax, 7-10
RETx register, 3-5
RND12 instruction, 15-13
RND20 instruction, 15-10
RND_MOD (rounding) bit
affected instructions, 9-18, 15-38, 15-45,
15-59
ASTAT register, 1-20
biased rounding, 2-23
rounding defined, 2-19
rounding mode, 2-25
RND option (multiplier results rounding),
2-19
RND (round to half-word) instruction,
15-77, C-94
ROM
external memory device,
internal memory space,
rotate operations instructions,
rotate (ROT) instruction, 14-21,
ROT...BY instruction,
ROT (rotate) instruction, 14-21,
rounding
behavior, 1-20
biased, 1-19, 2-19, 2-22
convergent, 1-19, 2-20
defined, 2-19
example, 2-19
instructions, 2-19
3-5
1-6
6-2
C-46
C-54
14-21
C-54