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Instruction Overview
Parallel Issue
The Core Synchronize instruction cannot be issued in parallel with other
instructions.
Example
Consider the following example code sequence.
if cc jump away_from_here ;
prediction */
csync ;
r0 = [p0] ;
In this example, the
not executed speculatively.
resolved and any entries in the processor store buffer have been flushed. In
addition, all speculative states or exceptions complete processing before
completes.
CSYNC
Also See
System Synchronize
Special Applications
Use
to enforce a strict execution sequence on loads and stores or to
CSYNC
conclude all transitional core states before reconfiguring the core modes.
For example, issue
(MMRs).
CSYNC
the data reaches the MMR before the next instruction is fetched.
Typically, the Blackfin processor executes all load instructions strictly in
the order that they are issued and all store instructions in the order that
they are issued. However, for performance reasons, the architecture relaxes
ordering between load and store operations. It usually allows load opera-
tions to access memory out of order with respect to store operations.
16-6
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* load */
instruction ensures that the load instruction is
CSYNC
ensures that the conditional branch is
CSYNC
before configuring memory-mapped registers
CSYNC
should also be issued after stores to MMRs to make sure
/* produces speculative branch
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