Table of Contents
Advertisement
Therefore, two-dimensional loops are supported directly in hardware,
consisting of an outer loop and a nested inner loop.
The outer loop is always represented by loop unit 0 (
while loop unit 1 (
To enable the two nested loops to end at the same instruction (
), loop unit 1 is assigned higher priority than loop unit 0. A loopback
LB0
caused by loop unit 1 on a particular instruction (
prevent loop unit 0 from looping back on that same instruction, even if
the address matches. Loop unit 0 is allowed to loop back only after the
loop count 1 is exhausted. The following example shows a two-dimen-
sional loop.
#define M 32
#define N 1024
P4 = M (Z);
P5 = N-1 (Z);
LSETUP ( lpo_start, lpo_end ) LCO = P4;
lpo_start:
MNOP || R2 = [I0++] || R3 = [I1++] ;
LSETUP (lpi_start, lpi_end) LC1 = P5;
lpi_start:
lpi_end:
R5 = R2 + R3;
R7 = R5 + R7 (NS) || [I0++] = R5;
lpo_end:
[I2++] = R7;
The example processes an M by N data structure. The inner loop is
unrolled and passes only N-1 times. The outer loop is not unrolled and
still provides room for optimization.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
LC1
LT1
R7 = 0;
R5 = R2 + R3 (NS) || R2 = [I0] || R3 = [I1++] ;
R7 = R5 + R7 (NS) || [I0++] = R5;
Program Sequencer
,
) manages the inner loop.
LB1
PC==LB1
,
,
)
LC0
LT0
LB0
equals
LB1
,
) will
LC1>=2
4-25
Advertisement
Table of Contents
