Analog Devices ADSP-BF53x Blackfin Reference page 911

Table C-21. Vector Operations Instructions (Sheet 5 of 33)
Instruction
and Version
Vector Add / Subtract
Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (CO)
Vector Add / Subtract
Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (CO, ASR)
Vector Add / Subtract
Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (CO, ASL)
Vector Add / Subtract
Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (SCO)
Vector Add / Subtract
Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (SCO, ASR)
Vector Add / Subtract
Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (SCO, ASL)
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 x x x 0 0 0 0 0 1
0xC401 1000—
0xC401 1FFF
0 0 0 1
1 1 0 0 0 1 0 x x x 0 0 0 0 0 1
0xC401 9000—
0xC401 9FFF
1 0 0 1
1 1 0 0 0 1 0 x x x 0 0 0 0 0 1
0xC401 D000—
0xC401 DFFF
1 1 0 1
1 1 0 0 0 1 0 x x x 0 0 0 0 0 1
0xC401 3000—
0xC401 3FFF
0 0 1 1
1 1 0 0 0 1 0 x x x 0 0 0 0 0 1
0xC401 B000—
0xC401 BFFF
1 0 1 1
1 1 0 0 0 1 0 x x x 0 0 0 0 0 1
0xC401 F000—
0xC401 FFFF
1 1 1 1
1 1 0 0 0 1 0 x x x 1 0 0 0 0 1
0xC421 0000—
0xC421 0FFF
0 0 0 0
Instruction Opcodes
Bin
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Dest 1 Dest 0 Source 0
Dreg # Dreg # Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
C-111