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Table C-17. Arithmetic Operations Instructions (Sheet 13 of 44)
Instruction
and Version
Multiply 16-Bit Operands
NOTE: When issuing compatible load/store instructions in parallel with a Multiply 16-Bit Operands
instruction, add 0x0800 0000 to the Multiply 16-Bit Operands opcode.
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (IH, M)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (FU)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (IS)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (S2RND)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (ISS2)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC374 0000—
1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0
0xC374 C1FF
Dreg
half
0xC20C 0000—
1 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0
0xC20C C1FF
Dreg
half
0xC28C 0000—
1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0
0xC28C C1FF
Dreg
half
0xC30C 0000—
1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0
0xC30C C1FF
Dreg
half
0xC22C 0000—
1 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0
0xC22C C1FF
Dreg
half
0xC32C 0000—
1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0
0xC32C C1FF
Dreg
half
0xC21C 0000—
1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0
0xC21C C1FF
Dreg
half
Instruction Opcodes
Bin
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
C-67
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