Index
data watchpoint address control
(WPDACTL) register,
data watchpoint address count value
(WPDACNTn) registers,
data watchpoint address (WPDAn)
registers,
21-10
DBGCTL (debug control) register,
DCB bus,
6-8
DCBS bit
recommended value,
when changing selection,
DCBS (L1 data cache bank select) bit,
6-25, 6-26, 6-29,
DCPLB address (DCPLB_ADDRx)
registers, 6-47,
6-59
DCPLB_ADDRx (DCPLB address)
registers, 6-47,
6-59
DCPLB data (DCPLB_DATAx) registers,
6-47,
6-57
DCPLB_DATAx (DCPLB data) registers,
6-47,
6-57
DCPLB_FAULT_ADDR (DCPLB fault
address) register,
6-63
DCPLB fault address
(DCPLB_FAULT_ADDR) register,
6-63
DCPLB_STATUS (DCPLB status)
register, 6-61,
6-62
DCPLB status (DCPLB_STATUS)
register, 6-61,
6-62
debug, MP, and emulation unit registers,
B-7
debug control (DBGCTL) register. See
DBGCTR
debug features,
21-1
DEC (instruction decode),
DEC stage,
4-9
deferring exception processing,
DEPOSIT (bit field deposit) instruction,
13-10
I-10
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
21-12
21-11
3-16
6-32
6-33
6-31
4-7
4-68
DF1 (data fetch 1),
4-7
DF2 (data fetch 2),
4-7
DF2 stage,
4-9
direct branch address,
4-11
direct-mapped, definition,
dirty, definition,
6-75
DIRTY bit,
6-42
disable alignment exception for load
(DISALGNEXCPT) instruction. See
DISALGNEXCPT
disable interrupts (CLI) instruction, 6-74,
16-13,
C-99
disabling interrupts, global,
DISALGNEXCPT (disable alignment
exception for load) instruction
cautions,
5-17
syntax,
18-6
table,
C-102
uses of,
5-16
divide primitive (DIVS, DIVQ)
instructions, 2-14, 2-34, 15-19,
DIVQ (divide primitive) instruction, 2-34,
15-19
DIVS (divide primitive) instruction, 2-34,
15-19
DMA bandwidth,
6-27
DMC[1:0] (L1 data memory configure)
field, 6-25, 6-27, 6-30,
DMEM_CONTROL (data memory
control) register, 6-24,
double-fault condition,
double word index (DW[1:0]) field,
DPMC (dynamic power management
controller)
Dreg_even
multiply and multiply-accumulate,
15-67
syntax,
9-3
Dreg_hi, 15-43, 15-58,
syntax, 8-45,
9-16
6-74
4-48
C-60
6-38
6-47
4-46
6-21
19-3
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