Table of Contents
Advertisement
L1 Data Memory
The
PORT_PREF0
non-cacheable L2 fetches. Cacheable fetches are always processed by the
data port physically associated with the targeted cache memory. Steering
DAG0, DAG1, and cache traffic to different ports optimizes performance
by keeping the queue to L2 memory full.
For optimal performance with dual DAG reads, DAG0 and DAG1
should be configured for different ports. For example, if
PORT_PREF0
grammed to 0.
The
bit provides some control over which addresses alias into the
DCBS
same set. This bit can be used to affect which addresses tend to remain res-
ident in cache by avoiding victimization of repetitively used sets. It has no
affect unless both Data Bank A and Data Bank B are serving as cache (bits
in this register are set to
DMC[1:0]
The
bit is used to enable/disable the 16 Cacheability Protection
ENDCPLB
Lookaside Buffers (CPLBs) used for data (see
6-29). Data CPLBs are disabled by default after reset. When disabled,
only minimal address checking is performed by the L1 memory interface.
This minimal checking generates an exception when the processor:
• Addresses nonexistent (reserved) L1 memory space
• Attempts to perform a nonaligned memory access
• Attempts to access MMR space either using DAG1 or when in
User mode
CPLBs must be disabled using this bit prior to updating their descriptors
(registers
DCPLB_DATAx
ing is weak (see
CPLBs should be preceded by a
When enabling or disabling cache or CPLBs, immediately follow
the write to
6-26
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
bit selects the data port used to process DAG0
is configured as 1, then
and
DCPLB_ADDRx
"Ordering of Loads and Stores" on page
CSYNC
with a
DMEM_CONTROL
PORT_PREF1
).
11
"L1 Data Cache" on page
). Note that since load store order-
instruction.
to ensure proper behavior.
SSYNC
should be pro-
6-67), disabling
Advertisement
Table of Contents
