Memory Transaction Model - Analog Devices ADSP-BF53x Blackfin Reference

Memory Transaction Model

Both internal and external memory locations are accessed in little endian
byte order. Figure 6-27
memory at address location addr. B0 refers to the least significant byte of
the 32-bit word.
DATA IN REGISTER
R0
Figure 6-27. Data Stored in Little Endian Order
Figure 6-28 shows 16- and 32-bit instructions stored in memory. The dia-
gram on the left shows 16-bit instructions stored in memory with the
most significant byte of the instruction stored in the high address (byte B1
in addr+1) and the least significant byte in the low address (byte B0 in
addr).
16-BIT INSTRUCTIONS
B1
16-BIT INSTRUCTIONS IN MEMORY
B1
addr+3
Figure 6-28. Instructions Stored in Little Endian Order
The diagram on the right shows 32-bit instructions stored in memory.
Note the most significant 16-bit half word of the instruction (bytes B3
and B2) is stored in the low addresses (addr+1 and addr), and the least sig-
nificant half word (bytes B1 and B0) is stored in the high addresses
(addr+3 and addr+2).
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
shows a data word stored in register
B3 B2 B1 B0
INST 0
B0
B0
B0 B1
addr+2
addr+1 addr
DATA IN MEMORY
B3 B2 B1
addr+2
addr+3 addr+1
32-BIT INSTRUCTIONS
INST 0
B3 B2 B1 B0
32-BIT INSTRUCTIONS IN MEMORY
B1 B0
B3
addr+2 addr+1
addr+3
Memory
and in
R0
B0
addr
B2
addr
6-65