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Instruction Watchpoint Address Count Registers (WPIACNTn)
For Memory-mapped
addresses, see
Table
21-5.
WPIACNT (Count Value)[15:0]
Figure 21-2. Instruction Watchpoint Address Count Registers
Table 21-5. Instruction Watchpoint Address Count Register
Memory-mapped Addresses
Register Name
WPIACNT0
WPIACNT1
WPIACNT2
WPIACNT3
WPIACNT4
WPIACNT5
WPIACTL Register
Three bits in the Instruction Watchpoint Address Control register
(
) control each instruction watchpoint.
WPIACTL
upper half of the register.
half of the register. For more information about the bits in this register,
see
"Instruction Watchpoints" on page
The bits in the
is set.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
X
X
X
X
X
X
X
X
Memory-mapped Address
0xFFE0 7080
0xFFE0 7084
0xFFE0 7088
0xFFE0 708C
0xFFE0 7090
0xFFE0 7094
Figure 21-4 on page 21-9
register have no effect unless the
WPIACTL
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
Figure 21-3
describes the lower
21-4.
Debug
Reset = Undefined
describes the
bit
WPPWR
21-7
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