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Arithmetic Logic Unit (ALU)
Table 2-9. ALU Instruction Summary
Instruction
Dreg = Dreg + Dreg ;
Dreg = Dreg – Dreg (S) ;
Dreg = Dreg + Dreg,
Dreg = Dreg – Dreg ;
Dreg_lo_hi = Dreg_lo_hi +
Dreg_lo_hi ;
Dreg_lo_hi = Dreg_lo_hi –
Dreg_lo_hi (S) ;
Dreg = Dreg +|+ Dreg ;
Dreg = Dreg +|– Dreg ;
Dreg = Dreg –|+ Dreg ;
Dreg = Dreg –|– Dreg ;
Dreg = Dreg +|+Dreg,
Dreg = Dreg –|– Dreg ;
Dreg = Dreg +|– Dreg,
Dreg = Dreg –|+ Dreg ;
Dreg = An + An,
Dreg = An – An ;
Dreg += imm7 ;
Dreg = ( A0 += A1 ) ;
Dreg_lo_hi = ( A0 += A1) ;
A0 += A1 ;
A0 –= A1 ;
DIVS ( Dreg, Dreg ) ;
DIVQ ( Dreg, Dreg ) ;
2-32
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
ASTAT Status Flags
AZ
AN
AC0
AC0_COPY
AC1
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AV0
AV1
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AV0S
AV1S
V_COPY
VS
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AQ
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