Analog Devices ADSP-BF53x Blackfin Reference page 191

In order for high priority interrupts to be serviced with the least latency
possible, the processor allows any high latency fill operation to be com-
pleted at the system level, while an interrupt service routine executes from
L1 memory. See
CLOCK
OTHER PROCESSORS
FETCH
INSTRUCTION
DATA
INTERRUPT
OCCURRING
HERE
BLACKFIN PROCESSOR
FETCH
INSTRUCTION
DATA
INTERRUPT
OCCURRING
HERE
Figure 4-10. Minimizing Latency in Servicing an ISR
If an instruction load operation misses the L1 instruction cache and gener-
ates a high latency line fill operation, then when an interrupt occurs, it is
not held off until the fill has completed. Instead, the processor executes
the interrupt service routine in its new context, and the cache fill opera-
tion completes in the background.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Figure 4-10.
SERVICED
HERE
Program Sequencer
SERVICED
HERE
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