Bytepack (Quad 8-Bit Pack) - Analog Devices ADSP-BF53x Blackfin Reference

Instruction Overview

BYTEPACK (Quad 8-Bit Pack)

General Form
dest_reg = BYTEPACK ( src_reg_0, src_reg_1 )
Syntax
Dreg = BYTEPACK ( Dreg, Dreg ) ;
Syntax Terminology
:
Dreg R7–0
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Quad 8-Bit Pack instruction packs four 8-bit values, half-word
aligned, contained in two source registers into one register, byte aligned as
shown in Table 18-22
Table 18-22. Source Registers Contain
src_reg_0:
src_reg_1:
Table 18-23. Destination Register Receives
dest_reg:
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
18-30 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
and Table
31................24 23................16
byte3
/* (b) */
18-23.
15..................8
byte1
byte3
byte2 byte1
7....................0
byte0
byte2
byte0