Analog Devices ADSP-BF53x Blackfin Reference page 682

Instruction Overview
Table 18-31. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
Options
The (R) syntax reverses the order of the source registers within the pair.
Typical high performance applications cannot afford the overhead of
reloading both register pair operands to maintain byte order for every cal-
culation. Instead, they alternate and load only one register pair operand
each time and alternate between the forward and reverse byte order ver-
sions of this instruction. By default, the low order bytes come from the
low register in the register pair. The (R) option causes the low order bytes
to come from the high register.
In the optional reverse source order case (for example, using the (R) syn-
tax), the only difference is the source registers swap places in their byte
ordering. Assume the source register pair contains the data shown in
Table 18-32.
Table 18-32. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
18-42 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
src_reg_pair_HI
byte7 byte6 byte5
byte5
byte6 byte5
src_reg_pair_LO
byte7 byte6 byte5
byte5
byte6 byte5
src_reg_pair_LO
byte4 byte3 byte2
byte3 byte2
byte4 byte3 byte2
byte4 byte3 byte2
byte4 byte3
src_reg_pair_HI
byte4 byte3 byte2
byte3 byte2
byte4 byte3 byte2
byte4 byte3 byte2
byte4 byte3
byte1 byte0
byte1 byte0
byte1
byte1 byte0
byte1 byte0
byte1