Instruction Overview
The instruction supports only biased rounding. The
register has no bearing on the rounding behavior of this instruction.
ASTAT
See
"Saturation" on page 1-17
See
"Rounding and Truncating" on page 1-19
ing behavior.
Flags Affected
The following flags are affected by this instruction:
•
is set if result is zero; cleared if nonzero.
AZ
•
is set if result is negative; cleared if non-negative.
AN
•
is set if result saturates; cleared if no saturation.
V
•
is set if
VS
All other flags are unaffected.
Required Mode
User & Supervisor
Parallel Issue
This instruction can be issued in parallel with specific other 16-bit
instructions. For details, see
Example
r1.l = r6+r7(rnd12) ;
r1.l = r6-r7(rnd12) ;
r1.h = r6+r7(rnd12) ;
r1.h = r6-r7(rnd12) ;
15-14
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for a description of saturation behavior.
is set; unaffected otherwise.
V
"Issuing Parallel Instructions" on page
bit in the
RND_MOD
for a description of round-
20-1.
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