DAG1 misaligned access,
DAG1 multiple CPLB hits,
DAG1 port preference (PORT_PREF1)
bit, 6-24,
6-25
DAG1 protection violation,
DAG (data address generator) register
addressing modes,
5-18
as processor section (table),
defined, 1-14,
2-6
description summary,
exceptions,
4-65
performance with reads,
register modification,
registers,
5-8
stalls,
4-9
support for branches,
dagreg, syntax,
9-3
data
flow,
2-1
memory stalls,
4-9
store format,
6-75
transfers,
2-8
watchpoints,
21-3
data, sign extending,
2-12
data, zero extending,
2-12
data[15:0] field, 6-23,
data[31:16] field, 6-23,
data[47:32] field, 6-22,
data[63:48] field, 6-22,
data address generator (DAG). See DAG
data address registers, initialization,
data address (WPDA[31:16]) field,
data arithmetic unit, diagram,
data bank access bit,
6-40
data banks, configuration,
data cache
access,
6-33
control instructions,
flush instruction,
C-101
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-66
4-66
4-66
C-3
C-3
6-26
5-15
4-3
6-42
6-42
6-41
6-41
5-4
21-11
1-2
6-30
6-37
data cache
invalidation,
6-38
L1 memory, 6-2,
6-29
data cacheability protection lookaside
buffer enable (ENDCPLB) bit, 6-25,
6-26, 6-30,
6-51
data cache line, states,
6-34
data cache line flush and invalidate
(FLUSHINV) instruction. See
FLUSHINV
data cache line invalidate instruction,
C-101
data cache lines, instructions,
data cache prefetch (PREFETCH)
instruction, 6-37, 17-3,
data cache select/address bit 14,
data fetch 1 (DF1),
4-7
data fetch 2 (DF2),
4-7
data formats,
2-4
to
2-5
binary multiplication,
table,
2-13
data/instruction access bit,
data memory, L1,
6-24
data memory control
(DMEM_CONTROL) register,
6-24,
6-47
data operations, CPLB,
data register file, 2-1, 2-2, 2-6, 2-7,
data registers
description, 1-13,
C-2
groups,
2-6
names,
3-4
data SRAM, L1,
6-27
data test command
(DTEST_COMMAND) register,
6-39
data test data (DTEST_DATAx) registers,
6-41, 6-42,
17-2
data test registers,
6-38
data types,
2-11
to
2-23
Index
(continued)
17-1
C-101
6-40
D-5
6-40
to
6-38
6-47
2-8
to
6-42
I-9
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