Analog Devices ADSP-BF53x Blackfin Reference page 63

I3 L3
I2 L2
I1 L1
I0 L0
DA1 32
DA0 32
32
RAB
SD 32
LD1 32
32
LD0 32
R7.H R7.L
R6.H R6.L
R5.H R5.L
R4.H R4.L
R3.H R3.L
R2.H R2.L
R1.H R1.H
R0.H R0.L
Figure 2-1. Processor Core Architecture
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
ADDRESS ARITHMETIC UNIT
B3 M3
B2 M2
B1 M1
DAG1
B0 M0
32
16
8
BARREL
SHIFTER
40
A0
32
32
DATA ARITHMETIC UNIT
Computational Units
DAG0
16
8 8
40
40 40
A1
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
ASTAT
SEQUENCER
ALIGN
8
DECODE
LOOP BUFFER
CONTROL
UNIT
2-3