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Reset State
The processor remains in the Idle state until a peripheral or external
device, such as a SPORT or the Real-Time Clock (RTC), generates an
interrupt that requires servicing.
In
Listing
3-3, core interrupts are disabled and the
cuted. When all the pending processes have completed, the core disables
its clocks. Since interrupts are disabled, Idle state can be terminated only
by asserting a
WAKEUP
ter" on page
4-34. (While not required, an interrupt could also be enabled
in conjunction with the
When the
WAKEUP
instruction enables interrupts again.
Example Code for Transition to Idle State
To transition to the Idle state, use code shown in
Listing 3-3. Transitioning to Idle State
CLI R0 ;
/* disable interrupts */
IDLE ;
/* drain pipeline and send core into IDLE state */
STI R0 ;
/* re-enable interrupts after wakeup */
Reset State
Reset state initializes the processor logic. During Reset state, application
programs and the operating system do not execute. Clocks are stopped
while in Reset state.
The processor remains in the Reset state as long as external logic asserts
the external
RESET
reset sequence and switches to Supervisor mode, where it executes code
found at the reset event vector.
3-10
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
signal. For more information, see
signal.)
WAKEUP
signal is asserted, the processor wakes up, and the
signal. Upon deassertion, the processor completes the
instruction is exe-
IDLE
"SIC_IWR Regis-
Listing
3-3.
STI
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