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buses leads to a better understanding of proper data flow for computa-
tions. Next, details about the processor's advanced parallelism reveal how
to take advantage of multifunction instructions.
Figure 2-1
shows the relationship between the Data Register File and the
computational units—multipliers, ALUs, and shifter.
Single function multiplier, ALU, and shifter instructions have unrestricted
access to the data registers in the Data Register File. Multifunction opera-
tions may have restrictions that are described in the section for that
particular operation.
Two additional registers, A0 and A1, provide 40-bit accumulator results.
These registers are dedicated to the ALUs and are used primarily for mul-
tiply-and-accumulate functions.
The traditional modes of arithmetic operations, such as fractional and
integer, are specified directly in the instruction. Rounding modes are set
from the
register, which also records status and conditions for the
ASTAT
results of the computational operations.
2-2
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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