Analog Devices ADSP-BF53x Blackfin Reference page 981

Table C-23. 32-Bit Opcode Instructions (Sheet 28 of 40)
Instruction
and Version
Quad 8-Bit Add
(Dreg, Dreg) = BYTEOP16P (Dreg_pair, Dreg_pair)
Quad 8-Bit Add
(Dreg, Dreg) = BYTEOP16P (Dreg_pair, Dreg_pair) (R)
Quad 8-Bit Subtract
(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair)
Quad 8-Bit Subtract
(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair) (R)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL, R)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL, R)
Dual 16-Bit Add / Clip
Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO)
Dual 16-Bit Add / Clip
Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO, R)
Quad 8-Bit Pack
Dreg = BYTEPACK (Dreg, Dreg)
Quad 8-Bit Unpack
(Dreg, Dreg) = BYTEUNPACK Dreg_pair
Quad 8-Bit Unpack
(Dreg, Dreg) = BYTEUNPACK Dreg_pair (R)
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (CO)
Vector Add / Subtract
Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (S)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0xC415 0000—
0xC415 0FFF
0xC415 2000—
0xC415 2FFF
0xC415 4000—
0xC415 4FFF
0xC415 6000—
0xC415 6FFF
0xC416 0000—
0xC416 0E3F
0xC416 2000—
0xC416 2E3F
0xC416 4000—
0xC416 6E3F
0xC416 6000—
0xC416 7E3F
0xC417 0000—
0xC417 0E3F
0xC417 2000—
0xC417 1E3F
0xC418 0000—
0xC418 0E3F
0xC418 4000—
0xC418 4FF8
0xC418 6000—
0xC418 6FF8
0xC421 0000—
0xC421 0FFF
0xC421 1000—
0xC421 1FFF
0xC421 2000—
0xC421 2FFF
C-181