Analog Devices ADSP-BF53x Blackfin Reference page 853

Table C-16. Shift / Rotate Operations Instructions (Sheet 8 of 9)
Instruction
and Version
Logical Shift
Dreg_lo = LSHIFT Dreg_lo BY Dreg_lo
Logical Shift
Dreg_lo = LSHIFT Dreg_hi BY Dreg_lo
Logical Shift
Dreg_hi = LSHIFT Dreg_lo BY Dreg_lo
Logical Shift
Dreg_hi = LSHIFT Dreg_hi BY Dreg_lo
Logical Shift
Dreg = LSHIFT Dreg BY Dreg_lo
Logical Shift
A0 = LSHIFT A0 BY Dreg_lo
Logical Shift
A1 = LSHIFT A1 BY Dreg_lo
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC600 8000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0
0xC600 8E3F
1 0 0 0 Dest.
0xC600 9000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0
0xC600 9E3F
1 0 0 1 Dest.
0xC600 A000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0
0xC600 AE3F
1 0 1 0 Dest.
0xC600 B000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0
0xC600 BE3F
1 0 1 1 Dest.
0xC602 8000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 1 0
0xC602 8E3F
1 0 0 0 Dest.
0xC603 4000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 1 1
0xC603 4038
0 1 0 0 0 0 0 x x x Source
0xC603 5000— 1 1 0 0 0 1 1 0 0 x x 0 0 0 1 1
0xC603 5038
0 1 0 1 0 0 0 x x x Source
Instruction Opcodes
Bin
x x x Source
Dreg # Dreg #
x x x Source
Dreg # Dreg #
x x x Source
Dreg # Dreg #
x x x Source
Dreg # Dreg #
x x x Source
Dreg # Dreg #
Dreg #
Dreg #
sh_mag
Dreg #
sh_mag
Dreg #
sh_mag
Dreg #
sh_mag
Dreg #
sh_mag
Dreg #
0 0 0
0 0 0
C-53