Analog Devices ADSP-BF53x Blackfin Reference page 503

The
dest_reg
For the
LSHIFT
, sign extended. The
Dreg_lo
tions use the entire 32 bits of magnitude.
The D-register versions of this instruction shift 16 or 32 bits for half-word
and word registers, respectively. The Accumulator versions shift all 40 bits
of those registers.
Forty-bit Accumulator values can be shifted by up to –32 to +31 bit
places.
Shift magnitudes that exceed the size of the destination register produce
all zeros in the result. For example, shifting a 16-bit register value by 20
bit places (a valid operation) produces 0x0000.
A shift magnitude of zero performs no shift operation at all.
The D-register versions of this instruction do not implicitly modify the
values. Optionally,
src_reg
. Doing this explicitly modifies the source register.
src_reg
Flags Affected
The P-register versions of this instruction do not affect any flags.
The versions of this instruction that send results to a
follows.
• is set if result is zero; cleared if nonzero.
AZ
• is set if result is negative; cleared if non-negative.
AN
• is cleared.
V
• All other flags are unaffected.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
and can be a 16-, 32-, or 40-bit register.
src_reg
instruction, the shift magnitude is the lower 6 bits of the
Dreg >>= Dreg
dest_reg
Shift/Rotate Operations
and
Dreg <<= Dreg
can be the same D-register as
Dreg
instruc-
set flags as
14-17