Example Code For Using Hardware Loops In An Isr - Analog Devices ADSP-BF53x Blackfin Reference

Hardware Loops
To avoid unnecessary penalty cycles, the loop hardware follows these
rules:
• Restoring
ware and causes a ten-cycle "replay" penalty.
• Restoring
respective loop counter register is zero.
• If is non-zero, every write to the
LCx
attempts to re-initialize the loop hardware and causes a ten-cycle
penalty.
In terms of performance, there is a difference depending on the order that
the loop registers are popped. For best performance, restore the
ters last. Furthermore, it is recommended that interrupt service routines
and global subroutines that contain hardware loops terminate their local
loops cleanly, that is, do not artificially break the loops and do not execute
return instructions within their loops. This guarantees that the
ters are 0 when

Example Code for Using Hardware Loops in an ISR

The following code shows the optimal method of saving and restoring
when using hardware loops in an interrupt service routine.
Listing 4-2. Saving and Restoring With Hardware Loops
:
lhandler
<Save other registers here>
[--SP] = LC0;
[--SP] = LB0;
[--SP] = LT0;
<Handler code here>
4-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
and registers always re-initializes the loop hard-
LC0 LC1
, , , and
LT0 LT1 LB0
and registers are popped.
LTx LBx
/* save loop 0 */
performs in a single cycle if the
LB1
and
LTx LBx
registers also
regis-
LCx
regis-
LCx