Table of Contents
Advertisement
2 COMPUTATIONAL UNITS
The processor's computational units perform numeric processing for DSP
and general control algorithms. The six computational units are two arith-
metic/logic units (ALUs), two multiplier/accumulator (multiplier) units, a
shifter, and a set of video ALUs. These units get data from registers in the
Data Register File. Computational instructions for these units provide
fixed-point operations, and each computational instruction can execute
every cycle.
The computational units handle different types of operations. The ALUs
perform arithmetic and logic operations. The multipliers perform
multiplication and execute multiply/add and multiply/subtract opera-
tions. The shifter executes logical shifts and arithmetic shifts and performs
bit packing and extraction. The video ALUs perform Single Instruction,
Multiple Data (SIMD) logical operations on specific 8-bit data operands.
Data moving in and out of the computational units goes through the Data
Register File, which consists of eight registers, each 32 bits wide. In opera-
tions requiring 16-bit operands, the registers are paired, providing sixteen
possible 16-bit registers.
The processor's assembly language provides access to the Data Register
File. The syntax lets programs move data to and from these registers and
specify a computation's data format at the same time.
Figure 2-1
provides a graphical guide to the other topics in this chapter.
An examination of each computational unit provides details about its
operation and is followed by a summary of computational instructions.
Studying the details of the computational units, register files, and data
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
2-1
Advertisement
Table of Contents
