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Figure 18-1. Absolute Difference (SAD) Calculations
Typical values for N are 8 and 16, corresponding to the video block size of
8x8 and 16x16 pixels, respectively. The 16-bit Accumulator registers limit
the pixel region or block size to 32x32 pixels.
The SAA instruction behavior is shown below.
Table 18-28. SAA Instruction Behavior
src_reg_0 a(i, j+3)
src_reg_1 b(i, j+3)
A1.H
+=| a(i, j+3)
-b(i, j+3) |
The Quad 8-Bit Subtract-Absolute-Accumulate instruction provides byte
alignment directly in the source register pairs
based on index registers
• The two LSBs of the
source register pair
• The two LSBs of the
source register pair
The relationship between the I-register bits and the byte alignment is
illustrated in
Table
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
N 1
N 1
–
∑
∑
SAD
=
i
0
j
=
=
a(i, j+2)
b(i, j+2)
A1.L +=| a(i, j+2)
- b(i, j+2) |
and
.
I0
I1
register determine the byte alignment for
I0
src_reg_0
register determine the byte alignment for
I1
src_reg_1
18-29.
Video Pixel Operations
–
a i j
( , ) b i j
–
( , )
0
a(i, j+1)
b(i, j+1)
A0.H +=| a(i, j+1)
- b(i, j+1) |
src_reg_0
(typically
).
R1:0
(typically
).
R3:2
a(i, j)
b(i, j)
A0.L +=| a(i, j)
- b(i, j) |
and
src_reg_1
18-37
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