Syscr Register; Software Resets And Watchdog Timer - Analog Devices ADSP-BF53x Blackfin Reference

System Reset and Powerup
System Software reset. See
Table 4-11, "Events That Cause Exceptions," on page 4-63
information.

SYSCR Register

The values sensed from the
Configuration register (
values are made available for software access and modification after the
hardware reset sequence. Software can modify only the No Boot on Soft-
ware Reset bit.
The various configuration parameters are distributed to the appropriate
destinations from
Blackfin Processor Hardware Reference for details.

Software Resets and Watchdog Timer

A software reset may be initiated in three ways:
• By the watchdog timer, if appropriately configured
• By setting the System Software Reset field in the Software Reset
register (see
• By the
RAISE1
The watchdog timer resets both the core and the peripherals. A System
Software reset results in a reset of the peripherals without resetting the
core and without initiating a booting sequence.
The System Software reset must be performed while executing
from Level 1 memory (either as cache or as SRAM).
When L1 instruction memory is configured as cache, make sure the Sys-
tem Software reset sequence has been read into the cache.
3-14 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
"Reset Interrupt" on page
pins are latched into the System Reset
BMODE
) upon the deassertion of the
SYSCR
. Refer to the Reset and Booting chapter of your
SYSCR
Figure 3-2 on page
instruction
4-46, and
3-16)
for further
pin. The
RESET