Instruction Cache Management; Instruction Cache Locking By Line - Analog Devices ADSP-BF53x Blackfin Reference

L1 Instruction Memory
For example:
• If Way3 is invalid and Ways0, 1, 2 are valid, Way3 is selected for
the new cache line.
• If Ways0 and 1 are invalid and Ways2 and 3 are valid, Way0 is
selected for the new cache line.
• If Ways2 and 3 are invalid and Ways0 and 1 are valid, Way2 is
selected for the new cache line.
When no invalid entries are found, the cache replacement logic uses an
LRU algorithm.

Instruction Cache Management

The system DMA controller and the core DAGs cannot access the instruc-
tion cache directly. By a combination of instructions and the use of core
MMRs, it is possible to initialize the instruction tag and data arrays indi-
rectly and provide a mechanism for instruction cache test, initialization,
and debug.
The coherency of instruction cache must be explicitly managed. To
accomplish this and ensure that the instruction cache fetches the
latest version of any modified instruction space, invalidate instruc-
tion cache line entries, as required.
See "Instruction Cache Invalidation" on page

Instruction Cache Locking by Line

The
CPLB_LRUPRIO
tion and Properties" on page
code remains resident in the instruction cache. When a cache line is filled,
the state of this bit is stored along with the line's tag. It is then used in
conjunction with the LRU (least recently used) policy to determine which
Way is victimized when all cache Ways are occupied when a new
6-16 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
bits in the
ICPLB_DATAx
6-45) are used to enhance control over which
6-18.
registers (see "Memory Protec-