Move Half To Full Word - Zero-Extended - Analog Devices ADSP-BF53x Blackfin Reference

Instruction Overview
Move Half to Full Word – Zero-Extended
General Form
dest_reg = src_reg (Z)
Syntax
Dreg = Dreg_lo (Z) ;
Syntax Terminology
:
Dreg R7–0
:
Dreg_lo R7–0.L
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length.
Functional Description
The Move Half to Full Word – Zero-Extended instruction converts an
unsigned half word (16 bits) to an unsigned word (32 bits).
The instruction copies the least significant 16 bits from a source register
into the lower half of a 32-bit register and zero-extends the upper half of
the destination register. The operation supports only D-registers. Zero
extension is appropriate for unsigned values. If used with signed values, a
small negative 16-bit value will become a large positive value.
9-10 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* (a) */