A0.X
A0
0000 0000
Destination
Register
A1.X
A1
0000 0000
Destination
Register
Figure 2-12. Multiplication of Fractional Operands
For example, this instruction uses fractional, unsigned operands:
R0.L = R1.L * R2.L (FU) ;
The instruction deposits the upper 16 bits of the multiply answer with
rounding and saturation into the lower half of R0, using MAC0. This
instruction uses unsigned integer operands:
R0.H = R2.H * R3.H (IU) ;
The instruction deposits the lower 16 bits of the multiply answer with any
required saturation into the high half of
R0 = R1.L * R2.L ;
Regardless of operand type, the preceding operation deposits 32 bits of the
multiplier answer with saturation into
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
A0.H
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
A1.H
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
R0
Computational Units
A0.L
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
A1.L
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
, using MAC1
R0
.
, using MAC0.
2-45
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