Analog Devices ADSP-BF53x Blackfin Reference page 979

Table C-23. 32-Bit Opcode Instructions (Sheet 26 of 40)
Instruction
and Version
Move Register Half
Dreg_lo = A1.X
Modify-Increment
Dreg = (A0 += A1)
Modify-Increment
Dreg_lo = (A0 += A1)
Modify-Increment
A0 += A1
Modify-Increment
A0 += A1 (W32)
Modify-Decrement
A0 –= A1
Modify-Decrement
A0 –= A1 (W32)
Add on Sign
Dreg_hi = Dreg_lo = SIGN (Dreg_hi) * Dreg_hi + SIGN (Dreg_lo) * Dreg_lo
Dual 16-Bit Accumulator Extraction with Addition
Dreg = A1.L + A1.H, Dreg = A0.L + A0.H
Round to Half Word
Dreg_lo = Dreg (RND)
Vector Search
(Dreg, Dreg) = SEARCH Dreg (GT)
Vector Search
(Dreg, Dreg) = SEARCH Dreg (GE)
Vector Search
(Dreg, Dreg) = SEARCH Dreg (LT)
Vector Search
(Dreg, Dreg) = SEARCH Dreg (LE)
Negate (Two's-Complement)
A0 = – A0
Negate (Two's-Complement)
A0 = – A1
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0xC40A 403F—
0xC40A 4E00
0xC40B 003F—
0xC40B 0E00
0xC40B 403F—
0xC40B 4E00
0xC40B 803F
0xC40B A03F
0xC40B C03F
0xC40B E03F
0xC40C 0000—
0xC40C 0E38
0xC40C 403F—
0xC40C 4FC0
0xC40C C000—
0xC40C CE38
0xC40D 0000—
0xC40D 2FFF
0xC40D 4000—
0xC40D 6FFF
0xC40D 8000—
0xC40D AFF8
0xC40D C000—
0xC40D EFF8
0xC40E 003F
0xC40E 403F
C-179