Table of Contents
Advertisement
• A status flag may be copied into
copied to a status flag.
• The
CC
comparison.
• The
CC
comparison.
• Some shifter instructions (rotate or
shift operand/result.
• Test and set instructions can set and clear the
These eight ways of accessing the
The branch is explicitly separated from the instruction that sets the arith-
metic flags. A single bit resides in the instruction encoding that specifies
the interpretation for the value of
true" or "branch on false."
The comparison operations have the form
pair of registers of the same type (for example, Data registers or Pointer
registers, or a single register and a small immediate constant). The small
immediate constant is a 3-bit (–4 through 3) signed number for signed
comparisons and a 3-bit (0 through 7) unsigned number for unsigned
comparisons.
The sense of
CC
equal to (
). There are also bit test operations that test whether a bit in a
<=
32-bit R-register is set.
Conditional Branches
The sequencer supports conditional branches. Conditional branches are
instructions whose execution branches or continues linearly, depend-
JUMP
ing on the value of the
address from the location of the instruction, plus an offset. The
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
flag bit may be set to the result of a Pointer register
flag bit may be set to the result of a Data register
is determined by equal (
bit. The target of the branch is a PC-relative
CC
Program Sequencer
, and the value in
CC
) use
BXOR
bit are used to control program flow.
CC
. The interpretation is to "branch on
CC
CC = expr
), less than (
==
may be
CC
as a portion of the
CC
bit.
CC
where expr involves a
), and less than or
<
4-19
Advertisement
Table of Contents
