System Interrupt Assignment Registers (Sic_Iarx) - Analog Devices ADSP-BF53x Blackfin Reference

Although this register can be read from or written to at any time (in
Supervisor mode), it should be configured in the reset initialization
sequence before enabling interrupts.

System Interrupt Assignment Registers (SIC_IARx)

The relative priority of peripheral interrupts can be set by mapping the
peripheral interrupt to the appropriate general-purpose interrupt level in
the core. The mapping is controlled by the System Interrupt Assignment
register settings, as detailed in the System Interrupt Appendix of the
Blackfin Processor Hardware Reference for your part. If more than one
interrupt source is mapped to the same interrupt, they are logically ORed,
with no hardware prioritization. Software can prioritize the interrupt pro-
cessing as required for a particular system application.
For general-purpose interrupts with multiple peripheral interrupts
assigned to them, take special care to ensure that software correctly
processes all pending interrupts sharing that input. Software is
responsible for prioritizing the shared interrupts.
These registers can be read from or written to at any time in Supervisor
mode. It is advisable, however, to configure them in the Reset interrupt
service routine before enabling interrupts. To prevent spurious or lost
interrupt activity, these registers should be written to only when all
peripheral interrupts are disabled.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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