Analog Devices ADSP-BF53x Blackfin Reference page 660

Instruction Overview
Table 18-11. Source Registers Contain
aligned_src_reg_0:
aligned_src_reg_1:
Table 18-12. Destination Registers Receive
dest_reg:
Arithmetic average (or mean) is calculated by summing the two operands,
then shifting right one place to divide by two.
The user has two options to bias the result–truncation or rounding up. By
default, the architecture rounds up the mean when the sum is odd. How-
ever, the syntax supports optional truncation.
See "Rounding and Truncating" on page 1-19
rounding and truncating behavior.
The bit in the
RND_MOD
behavior of this instruction.
The only valid input source register pairs are
The Quad 8-Bit Average – Byte instruction provides byte alignment
directly in the source register pairs
index registers
• The two LSBs of the
source register pair
• The two LSBs of the
source register pair
18-20 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31................24 23................16
y3
z3
31................24 23................16
avg(y3, z3) avg(y2, z2)
register has no bearing on the rounding
ASTAT
and .
I0 I1
register determine the byte alignment for
I0
src_reg_0
register determine the byte alignment for
I1
src_reg_1
15..................8
y2 y1
z2 z1
15..................8
avg(y1, z1)
for a description of biased
and
R1:0
and
src_reg_0 src_reg_1
(typically ).
R1:0
(typically ).
R3:2
7....................0
y0
z0
7....................0
avg(y0, z0)
.
R3:2
based on