Analog Devices ADSP-BF53x Blackfin Reference page 337

where:
• is the destination register. (
Dest
• is the first source register on the right-hand side of the
Src_1
equation.
• is the second source register.
Src_2
Indirect and post-increment index addressing supports customized indi-
rect address cadence. The indirect, post-increment index version must
have separate P-registers for the input operands. If a common Preg is used
for the inputs, the auto-increment feature does not work.
Flags Affected
None
Required Mode
User & Supervisor
Parallel Issue
The 16-bit versions of this instruction can be issued in parallel with spe-
cific other instructions.
Instructions" on page 20-1.
The 32-bit versions of this instruction cannot be issued in parallel with
other instructions.
Example
r3 = [ p0 ] ;
r7 = [ p1 ++ ] ;
r2 = [ sp -- ] ;
r6 = [ p2 + 12 ] ;
r0 = [ p4 + 0x800C ] ;
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Dreg
For more information, see "Issuing Parallel
Load / Store
in the syntax example).
8-13