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Working With Memory
Atomic Operations
The processor provides a single atomic operation:
tions are used to provide noninterruptible memory operations in support
of semaphores between tasks. The
addressed memory half word, tests whether the low byte is zero, and then
sets the most significant bit (MSB) of the low memory byte without
affecting any other bits. If the byte is originally zero, the instruction sets
the
bit. If the byte is originally nonzero, the instruction clears the
CC
bit. The sequence of this memory transaction is atomic—hardware bus
locking insures that no other memory operation can occur between the
test and set portions of this instruction. The
interrupted by the core. If this happens, the
cuted again upon return from the interrupt.
The
instruction can address the entire 4G byte memory space,
TESTSET
but should not target on-core memory (L1 or MMR space) since atomic
access to this memory is not supported.
The memory architecture always treats atomic operations as cache inhib-
ited accesses even if the CPLB descriptor for the address indicates cache
enabled access. However, executing
regions of memory is not recommended since the architecture cannot
guarantee a cacheable location of memory is coherent when the
instruction is executed.
Memory-mapped Registers
The MMR reserved space is located at the top of the memory space
(0xFFC0 0000). This region is defined as non-cacheable and is divided
between the system MMRs (0xFFC0 0000–0xFFE0 0000) and core
MMRs (0xFFE0 0000–0xFFFF FFFF).
Like non-memory mapped registers, the core MMRs connect to the 32-bit
wide Register Access Bus (RAB). They operate at
6-72
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
TESTSET
instruction loads an indirectly
TESTSET
TESTSET
TESTSET
operations on cacheable
TESTSET
CCLK
. Atomic opera-
CC
instruction can be
instruction is exe-
TESTSET
frequency.
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