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16-Bit Instructions
Table 20-2. 32-Bit DSP Instructions (Cont'd)
Instruction Name
Video Pixel Operations
ALIGN8, ALIGN16, ALIGN24
DISALGNEXCPT
Load)
SAA (Quad 8-Bit Subtract-Absolute-Accumulate)
Dual 16-Bit Accumulator Extraction with Addition
BYTEOP16P (Quad 8-Bit Add)
BYTEOP16M (Quad 8-Bit Subtract)
BYTEOP1P (Quad 8-Bit Average – Byte)
BYTEOP2P (Quad 8-Bit Average – Half-Word)
BYTEOP3P (Dual 16-Bit Add / Clip)
BYTEPACK (Quad 8-Bit Pack)
BYTEUNPACK (Quad 8-Bit Unpack)
16-Bit Instructions
The two16-bit instructions in a multi-issue instruction must each be from
Group1 and Group2 instructions shown in
The following additional restrictions also apply to the 16-bit instructions
of the multi-issue instruction.
• Only one of the 16-bit instructions can be a store instruction.
• If the two 16-bit instructions are memory access instructions, then
both cannot use P-registers as address registers. In this case, at least
one memory access instruction must be an I-register version.
20-6
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(Byte Align)
(Disable Alignment Exception for
Notes
Table 20-3
and
Table
20-4.
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