Introduction; Core Architecture - Analog Devices ADSP-BF53x Blackfin Reference

1 INTRODUCTION

This ADSP-BF53x/BF56x Blackfin Processor Programming Reference pro-
vides details on the assembly language instructions used by the Micro
Signal Architecture (MSA) core developed jointly by Analog Devices, Inc.
and Intel Corporation. This manual is applicable to all ADSP-BF53x and
ADSP-BF56x processor derivatives. With the exception of the first-gener-
ation ADSP-BF535 processor, all devices provide an identical core
architecture and instruction set. Specifics of the ADSP-BF535 processor
are highlighted where applicable and are summarized in
Dual-core derivatives and derivatives with on-chip L2 memory have
slightly different system interfaces. Differences and commonalities at a
global level are discussed in
of the system architecture beyond the Blackfin core, refer to the specific
Hardware Reference Manual for your derivative. This section points out
some of the conventions used in this document.
The Blackfin processor combines a dual MAC signal processing engine,
an orthogonal RISC-like microprocessor instruction set, flexible Single
Instruction, Multiple Data (SIMD) capabilities, and multimedia features
into a single instruction set architecture.

Core Architecture

The Blackfin processor core contains two 16-bit multipliers, two 40-bit
accumulators, two 40-bit arithmetic logic units (ALUs), four 8-bit video
ALUs, and a 40-bit shifter, shown in
32-bit data from the register file.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Chapter 6, "Memory."
Figure 1-1. The process 8-, 16-, or
Appendix A.
For a full description
1-1