Move Register Half - Analog Devices ADSP-BF53x Blackfin Reference

Move Register Half

General Form
dest_reg_half = src_reg_half
dest_reg_half = accumulator (opt_mode)
Syntax
A0.X = Dreg_lo ;
1
(b) */
A1.X = Dreg_lo ;
(b) */
Dreg_lo = A0.X ;
nificant 16 bits of Dreg (b) */
Dreg_lo = A1.X ;
nificant 16 bits of Dreg (b) */
A0.L = Dreg_lo ;
least significant 16 bits of A0.W (b) */
A1.L = Dreg_lo ;
least significant 16 bits of A1.W (b) */
A0.H = Dreg_hi ;
significant 16 bits of A0.W (b) */
A1.H = Dreg_hi ;
significant 16 bits of A1.W (b) */
1
The Accumulator Extension registers A0.X and A1.X are defined only for the 8 low-order bits 7
through 0 of A0.X and A1.X. This instruction truncates the upper byte of Dreg_lo before moving the
value into the Accumulator Extension register (A0.X or A1.X).
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* least significant 8 bits of Dreg into A0.X
/* least significant 8 bits of Dreg into A1.X
/* 8-bit A0.X, sign-extended, into least sig-
/* 8-bit A1.X, sign-extended, into least sig-
/* least significant 16 bits of Dreg into
/* least significant 16 bits of Dreg into
/* most significant 16 bits of Dreg into most
/* most significant 16 bits of Dreg into most
Move
9-15