Multiply 16-Bit Operands - Analog Devices ADSP-BF53x Blackfin Reference

Multiply 16-Bit Operands

General Form
dest_reg = src_reg_0 * src_reg_1 (opt_mode)
Syntax
Multiply-And-Accumulate Unit 0 (MAC0)
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (opt_mode_1) ;
result into the destination lower half-word register (b) */
Dreg_even = Dreg_lo_hi * Dreg_lo_hi (opt_mode_2) ;
result (b) */
Multiply-And-Accumulate Unit 1 (MAC1)
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (opt_mode_1) ;
result into the destination upper half-word register (b) */
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (opt_mode_2) ;
result (b) */
Syntax Terminology
:
Dreg R7–0
:
Dreg_lo R7–0.L
:
Dreg_hi R7–0.H
:
Dreg_lo_hi R7–0.L
: Optionally
opt_mode_1
. Optionally,
(IH)
with any of these other options. When used together, the option flags
must be enclosed in one set of parentheses and separated by a comma.
Example:
(M, IS)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
R7–0.H
, ,
(FU) (IS)
can be used with MAC1 versions either alone or
(M)
Arithmetic Operations
, , ,
(IU) (T) (TFU) (S2RND)
/* 16-bit
/* 32-bit
/* 16-bit
/* 32-bit
, or
(ISS2)
15-43