Performance Monitoring Unit - Analog Devices ADSP-BF53x Blackfin Reference

Listing 21-1. Recreating the Execution Trace in Memory
[--sp] = (r7:7, p5:2); /* save registers used in this routine */
p5 = 32; /* 32 reads are needed to empty TBUF */
p2.l = buf;
software trace buffer */
p2.h = buf;
location for subsequent trace dumps */
p4 = [p2++];
the buf header */
p3.l = TBUF & 0xffff;
p3.h = TBUF >> 16;
lsetup(loop1_start, loop1_end) lc0 = p5;
loop1_start: r7 = [p3];
loop1_end: [p4++] = r7;
[p2] = p4; /* pointer to the next available buf location is
saved in the header of buf */
(r7:7, p5:3) = [sp++];

Performance Monitoring Unit

Two 32-bit counters, the Performance Monitor Counter registers
( ) and the Performance Control register (
PFCNTR[1:0]
number of occurrences of an event from within a processor core unit dur-
ing a performance monitoring period. These registers provide feedback
indicating the measure of load balancing between the various resources on
the chip so that expected and actual usage can be compared and analyzed.
In addition, events such as mispredictions and hold cycles can also be
monitored.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* pointer to the header (first location) of the
/* the header stores the first available empty buf
/* get the first available empty buf location from
/* low 16 bits of TBUF */
/* high 16 bits of TBUF */
/* read from TBUF */
/* write to memory and increment
/* restore saved registers */
Debug
*/
), count the
PFCTL
21-19