Analog Devices ADSP-BF53x Blackfin Reference page 183

To determine when to service an interrupt, the controller logically ANDs
the three quantities in
level.
Servicing the highest priority interrupt involves these actions:
1. The interrupt vector in the Event Vector Table (EVT) becomes the
next fetch address.
On an interrupt, most instructions currently in the pipeline are
aborted. On a service exception, all instructions after the excepting
instruction are aborted. On an error exception, the excepting
instruction and all instructions after it are aborted.
2. The return address is saved in the appropriate return register.
The return register is
for NMIs, and
address of the instruction after the last instruction executed from
normal program flow.
3. Processor mode is set to the level of the event taken.
If the event is an NMI, exception, or interrupt, the processor mode
is Supervisor. If the event is an emulation exception, the processor
mode is Emulation.
4. Before the first instruction starts execution, the corresponding
interrupt bit in
is set.
Bit
IPEND[4]
address in
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, , and the current processor priority
ILAT IMASK
for interrupts,
RETI
for debug emulation. The return address is the
RETE
is cleared and the corresponding bit in
ILAT
is also set to disable all interrupts until the return
is saved.
RETI
Program Sequencer
for exceptions,
RETX RETN
IPEND
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