Analog Devices ADSP-BF53x Blackfin Reference page 851

Table C-16. Shift / Rotate Operations Instructions (Sheet 6 of 9)
Instruction
and Version
Logical Shift
Dreg_lo = Dreg_hi >> uimm4
Logical Shift
Dreg_hi = Dreg_lo >> uimm4
Logical Shift
Dreg_hi = Dreg_hi >> uimm4
Logical Shift
Dreg_lo = Dreg_lo << uimm4
Logical Shift
Dreg_lo = Dreg_hi << uimm4
Logical Shift
Dreg_hi = Dreg_lo << uimm4
Logical Shift
Dreg_hi = Dreg_hi << uimm4
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC680 9180— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 9FFF
1 0 0 1 Dest.
0xC680 A180— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 AFFF
1 0 1 0 Dest.
0xC680 B180— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 BFFF
1 0 1 1 Dest.
0xC680 8000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 8E7F
1 0 0 0 Dest.
0xC680 9000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 9E7F
1 0 0 1 Dest.
0xC680 A000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 AE7F
1 0 1 0 Dest.
0xC680 B000— 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0
0xC680 BE7F
1 0 1 1 Dest.
Instruction Opcodes
Bin
2's comp. of
Dreg # uimm4
2's comp. of
Dreg # uimm4
2's comp. of
Dreg # uimm4
uimm4
Dreg #
uimm4
Dreg #
uimm4
Dreg #
uimm4
Dreg #
Source
Dreg #
Source
Dreg #
Source
Dreg #
Source
Dreg #
Source
Dreg #
Source
Dreg #
Source
Dreg #
C-51